{"id":"e29fbc0e-0b0f-4018-b8cb-fe8eee01d1f9","title":"ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham","company":{"id":"c50b3607-4ab3-4e80-807b-d17fca6c3c88","name":"Qualcomm","website":"https://careers.qualcomm.com","url":"https://yesjob-web.pages.dev/companies/c50b3607-4ab3-4e80-807b-d17fca6c3c88"},"url":"https://yesjob-web.pages.dev/jobs/e29fbc0e-0b0f-4018-b8cb-fe8eee01d1f9","apply_url":"https://careers.qualcomm.com/careers/job/446720501243","status":"open","location":"Vancouver, British Columbia, Canada","locations":[{"city":"Vancouver","region":"BC","country":"CA"},{"city":"Markham","region":"ON","country":"CA"}],"workplace":"onsite","remote_eligible_countries":[],"employment_types":[],"work_auth_required":"unspecified","term":null,"salary_cad_per_year":null,"languages_required":[],"seniority":null,"first_seen_at":"2026-11-05T19:11:06.103Z","last_seen_at":"2026-11-07T05:58:05.828Z","salary_text":null,"summary":"- ASIC design verification role at Qualcomm Canada ULC, listed in Vancouver, BC or Markham, ON; pre-silicon work with SystemVerilog-UVM, formal verification and UPF.\n- Minimum: bachelor's in engineering/science plus 2+ years of ASIC design/verification experience; new grads with relevant co-op, intern or PEY experience are noted as qualifying.\n- Pay range listed as $108,000.00 - $158,000.00; work authorization and employment type are not stated.\n- Workplace model (onsite/hybrid) is not explicitly stated in the description.","sources":["https://careers.qualcomm.com/careers/job/446720501243"]}