{"id":"2b7940d3-4de4-4e5c-aa0c-4803523db5dc","title":"Design Verification Engineer — Memory Subsystem (Vancouver)","company":{"id":"c50b3607-4ab3-4e80-807b-d17fca6c3c88","name":"Qualcomm","website":"https://careers.qualcomm.com","url":"https://yesjob-web.pages.dev/companies/c50b3607-4ab3-4e80-807b-d17fca6c3c88"},"url":"https://yesjob-web.pages.dev/jobs/2b7940d3-4de4-4e5c-aa0c-4803523db5dc","apply_url":"https://careers.qualcomm.com/careers/job/446720445564","status":"open","location":"Vancouver, British Columbia, Canada","locations":[{"city":"Vancouver","region":"BC","country":"CA"}],"workplace":"onsite","remote_eligible_countries":[],"employment_types":[],"work_auth_required":"unspecified","term":null,"salary_cad_per_year":{"max":158000,"min":108000},"languages_required":[],"seniority":null,"first_seen_at":"2026-11-05T19:11:06.103Z","last_seen_at":"2026-11-06T11:49:37.188Z","salary_text":null,"summary":"- Design Verification Engineer for Qualcomm's memory subsystem team in Vancouver, BC (Qualcomm Canada ULC); focuses on memory controllers, DDR/LPDDR/HBM interfaces and PHY-related logic.\n- Requires 3+ years of ASIC/SoC/IP verification experience, a Bachelor's or Master's in an engineering or CS field, and hands-on Verilog, SystemVerilog, UVM and SVA skills.\n- Posting does not state employment type, work arrangement (onsite/hybrid/remote) or work authorization; check with the employer before applying.\n- Salary listed as $108,000–$158,000 (currency not explicitly stated; CAD assumed from Canadian location).","sources":["https://careers.qualcomm.com/careers/job/446720445564"]}